36
2012-2013
High Speed FPGA Design for Simple Multiplier Using Vedic Mathematics
Team
- Nazia Abdul Majeed Isub Saheb
4MT09EC050 - Pooja Prabhu
4MT09EC056 - Prajna Upadhyaya
4MT09EC058 - Ranjitha Shenoy
4MT09EC064
Advisor
Mr. Mahesh P. K.
(Associate Professor, Dept. of E and C, MITE, Moodbidri)
Department & College
Dept. of Electronics and Communication Engineering,
Mangalore Institute of Technology and Engineering, Moodbidri